1. Field of the Invention
The present invention relates to a method of measuring a propagation delay time of a transmission path to be connected to a semiconductor integrated circuit under test in a semiconductor integrated circuit testing apparatus and to a semiconductor integrated circuit testing apparatus using this method. More particularly, the present invention relates to a propagation delay time measuring method which is capable of measuring, in a short time duration and with high accuracy, a propagation delay time of a transmission path or line for a test pattern signal and a propagation delay time of a transmission path or line for a response signal, both the transmission paths being connected to a semiconductor integrated circuit which operates at high speed or rate and has its input terminal and its output terminal used in common, and relates to a semiconductor integrated circuit testing apparatus which is capable of accurately testing a semiconductor integrated circuit of this type using the aforesaid method.
2. Description of the Related Art
As is well known, in this technical field, a semiconductor integrated circuit (hereinafter referred to as IC) is called a logic IC in which a logical circuit portion (logic portion) is dominant or a memory IC in which a memory portion is dominant. In addition, an IC in which a logic portion and a memory portion are present in mixture on one chip is called a systematic LSI (Systematic Large Scale Integrated Circuit) or the like. FIG. 3 shows a general configuration of a semiconductor integrated circuit testing apparatus (hereinafter referred to as IC testing apparatus) which has conventionally been used for testing and measuring these ICs. This IC testing apparatus TES comprises, roughly speaking, a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a group of drivers (hereinafter referred to as a driver group) 116, a group of analog level comparators (hereinafter referred to as a comparator group) 117, a failure analysis memory 118, a failure relief processor 118A, a response time measuring device 120, a logical amplitude reference voltage source 121, a comparison reference voltage source 122, and a device power supply 123.
The main controller 111 is generally constituted by a computer system, has a test program PM created by a user (programmer) and previously stored therein, and controls the entire IC testing apparatus in accordance with the test program PM. The main controller 111 is connected, via a tester bus BUS, to the pattern generator 112, the timing generator 113, the failure analysis memory 118, the failure relief processor 118A, the response time measuring device 120, the logical amplitude reference voltage source 121, the comparison reference voltage source 122, the device power supply 123, and the like.
An IC to be tested (IC under test: DUT) 119 is mounted on a test head (not shown) constructed separately from the IC testing apparatus proper. Usually, on the top portion of the test head is mounted a member called a xe2x80x9cperformance boardxe2x80x9d, and a predetermined number of IC sockets are mounted on the performance board. Consequently, the IC under test 119 is mounted on an associated one of these IC sockets. In addition, a printed board called xe2x80x9cpin cardxe2x80x9d in this technical field is accommodated in the test head. Usually, circuits including a driver from the driver group 116 and a comparator from the comparator group 117 of the IC testing apparatus TES are formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and handling apparatus called xe2x80x9chandlerxe2x80x9d in this technical field, and is electrically connected to the IC testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
Further, the pin cards on which circuits including the driver from driver group 116 and the comparator from comparator group 117 of the IC testing apparatus TES and the like are formed is also called xe2x80x9cpin electronics partxe2x80x9d in this technical field. This pin electronics part is comprised of many pin electronics circuits one being provided for one of the terminal pins of the IC under test 119.
First of all, before starting the test of an IC, various kinds of data are set from the main controller 111. After the various kinds of data have been set, the test of the IC is started. When the main controller 111 issues a test start instruction to the pattern generator 112, the pattern generator 112 starts to generate a pattern. Accordingly, the time point when the pattern generator 112 starts to generate the pattern is the start time point of the test. The pattern generator 112 supplies test pattern data to the waveform formatter 114 in accordance with the test program. On the other hand, the timing generator 113 generates a timing signal (clock pulse) for controlling operating timings of the waveform formatter 114, the logical comparator 115, and the like.
The waveform formatter 114 converts the test pattern data supplied from the pattern generator 112 into a test pattern signal having a real waveform. This test pattern signal is applied to the IC under test (generally called xe2x80x9cDUTxe2x80x9d) 119 via the driver group 116 which voltage-amplifies the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source 121. It is to be noted here that in case the IC under test 119 is a memory IC or a memory portion of a systematic LSI is tested or the like, the test pattern signal is stored in a predetermined memory cell of the IC under test 119 and the stored content is read out therefrom in a read cycle performed later. On the contrary, in case the IC under test is a logic IC or a logic portion of a systematic LSI is tested or the like, the result of a logical operation of the test pattern signal is read out from the IC under test 119 as a response signal.
A response signal read out from the IC under test 119 is compared with a reference voltage supplied from the comparison reference voltage source 122 in the comparator group 117 which in turn determines whether or not the response signal has a predetermined logical level, that is, whether or not the response signal has a logical H (logical high) voltage or a logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator 115 where the response signal is compared with an expected value pattern signal outputted from the pattern generator 112 so that whether the IC under test 119 has outputted a normal response signal or not can be determined.
In case the IC under test 119 is a memory IC or a memory portion of a systematic LSI is tested or the like, if the response signal does not coincide with the expected value pattern signal, a decision is rendered that a memory cell having an address of the IC under test 119 from which that response signal has been read out is defective (failure), and a failure signal indicating that fact is generated from the logical comparator 115. Usually, when a failure signal is generated, a failure data (generally logical xe2x80x9c1xe2x80x9d signal) being applied to a data input terminal of the failure analysis memory 118 is enabled to be written in the memory, and the failure data is stored in an address of the failure analysis memory 118 specified by an address signal supplied to the failure analysis memory 118 at that time. Generally, since an address signal that is the same as the address signal applied to the IC under test 119 is applied to the failure analysis memory 118, the failure data is stored in an address of the failure analysis memory 118 that is the same as the address of the IC under test 119.
On the contrary, when the response signal coincides with the expected value pattern signal, a memory cell of the address of the IC under test 119 from which the response signal has been read out is determined to be normal (not defective), and a pass signal indicating that fact is generated. Usually, this pass signal is not stored in the failure analysis memory 118.
After the test has been completed, the failure data stored in the failure analysis memory 118 are read out therefrom into the failure relief processor 118A in which it is determined, for example, whether the relief of a failure memory cell or cells of the tested IC 119 is possible or not.
On the other hand, in case the IC under test 119 is a logic IC or a logic portion of a systematic LSI is tested or the like, if the response signal does not coincide with the expected value pattern signal, the test pattern signal from which that response signal has resulted, the address at which that test pattern signal has been generated, the logical data outputted from the pin of the IC under test 119 from which that response signal has been outputted, the expected value pattern data at that time, and the like are stored in the failure analysis memory 118. After the test has been completed, these stored data are utilized in an analysis of the cause of the failure occurring mechanism, an evaluation of the LSI, and the like.
The response time measuring device 120 is provided to measure a time interval from a timing that a read command or a response command is given to the IC under test 119 to a timing that the IC under test 119 actually outputs a response signal. Accordingly, the response time measuring device 120 can measure a response rate or speed of the IC under test 119.
The operation for detecting the timing when the IC under test 119 has outputted a response signal is performed in the comparator group 117. Specifically explaining, the timing when a response signal has been outputted is detected by applying a strobe pulse to each level comparator (hereinafter referred to as comparator) in the comparator group 117 and detecting whether the logical state of an output terminal (which also serves as an input terminal in the drawing) of the IC under test 119 is inverted or not at the timing when the strobe pulse has been applied.
For this reason, in case of measuring a response time of the IC under test 119, a plurality of test cycles are performed to measure the response time. That is, each time the IC under test 119 is set to a read cycle, the timing of application of a strobe pulse to the comparator group 117 is shifted by a predetermined phase in regular sequence in the direction of, for example, lagging in phase from the initial phase position of a test cycle constituting the reference test cycle, thereby to detect when the logical state of an output terminal of the IC under test 119 is inverted from logical L to logical H state or from logical H to logical L state. The time duration between the phase position of the strobe pulse having been applied at the time point when the logical state has been inverted and the initial phase position is detected as the response time.
Further, it is illustrated in FIG. 3 such that a test pattern signal outputted from the driver group 116 is applied only to one terminal 119A which serves as an input terminal and also as an output terminal of the IC under test 119, and a response signal from the one input/output terminal 119A of the IC under test 119 is supplied to the comparator group 117. However, in reality, the number of drivers provided in the driver group 116 is equal to the number of input/output terminals, for example 512, of the IC under test 119. Similarly, the number of comparators provided in the comparator group 117 is equal to the number of drivers (for example, 512).
From the above description, the outline of the operation of the IC testing apparatus TES would be understood. In recent years, a for ICs operating at higher speed has increased, and many high-speed ICs have been provided. As a result, the IC testing apparatus TES has been also required to operate at higher speed.
Here, problems occurring in case of testing high-speed ICs will be discussed. First, one problem occurs in the IC driving method for applying a test pattern signal to the IC under test 119 from the driver group 116. This problem occurs where a terminal of the IC under test 119 serves as an input terminal as well as an output terminal as shown in FIG. 3. Hereinafter, the terminal serving as an input terminal as well as an output terminal is referred to as an I/O pin.
The reason thereof will be explained with reference to FIG. 4. FIG. 4 shows a pin electronics circuit for one I/O pin of the IC under test 119, and the pin electronics circuit includes one driver DR and one comparator CP. An input terminal of the comparator CP is connected to an output terminal of the driver DR, and the common connection point P is connected to the I/O pin 119A of the IC under test 119 through a cable BL. Accordingly, the pin electronics circuit is constructed such that an operation for applying a test pattern signal to the I/O pin 119A of the IC under test 119 and an operation for taking a response signal from the I/O pin 119A of the IC under test 119 into the comparator CP are performed through the one cable BL. Further, in FIG. 4, a reference character VT indicates a termination voltage. This termination voltage VT is set to the median value of the amplitude of a test pattern signal outputted from the driver DR.
In the above circuit configuration, if a propagation delay time Tpd of the test pattern signal propagating through the cable BL is assumed to be Ta (Tpd=Ta), in the read cycle, a response signal D0 is delayed by the propagation delay time Ta of the cable BL as shown in FIG. 5B, and is then supplied to the input terminal of the comparator CP. Further, in FIG. 5, a reference character T denotes a test cycle, W denotes a write cycle, and R denotes a read cycle.
In order to supply the test pattern signal PAT to the I/O pin 119A from the beginning of the write cycle W, as shown in FIG. 5D, the test pattern signal PAT must be outputted from the driver DR at the time point preceding the starting time point of the write cycle W by the time duration equal to the propagation delay time Ta.
When the test pattern signal PAT is outputted from the driver DR at the time point preceding by a time duration equal to the propagation delay time Ta, the test pattern signal PAT is immediately supplied to the input terminal of the comparator CP. As a result, the comparator CP cannot acquire a response signal D0 from the IC under test 119 immediately after the driver DR has outputted the test pattern signal PAT. The time duration when the comparator CP cannot acquire a response signal D0 from the IC under test 119 is generally called a dead time DT. As is apparent from FIGS. 5B and 5D, the dead time DT in this case continues from the starting time point of application of the test pattern signal PAT until the ending time point of the response signal D0, and hence the dead time DT becomes twice the propagation delay time Ta of the cable BL.
The comparator CP determines the acquisition of a response signal D0 depending on the timing of application of a strobe pulse STB (refer to FIG. 5C). As mentioned above, the response time measuring device 120 detects a timing when the IC under test 119 starts to output a response signal D0 by shifting the timing of application of a strobe pulse STB by a predetermined phase in regular sequence for each test cycle throughout the entire time range in which a response signal is present, and measures a response time of the IC under test 119 to determine whether the response of the IC under test 119 is fast or slow.
Therefore, if the dead time DT mentioned above should exist, a response time of the IC under test 119 cannot be measured during the dead time DT, and hence there occurs a problem that a test for determining the operating speed cannot be carried out. Particularly, since the comparator CP cannot correctly acquire a response signal D0 during the dead time DT, whether or not the IC under test 119 correctly operates cannot be determined during the dead time DT.
In case of operating the IC under test 119 at high speed, the read cycle R and the write cycle W shown in FIG. 5A must be repeated at high speed. Accordingly, the existence of the dead time DT results in a big obstacle in materializing a high-speed testing.
In order to overcome this drawback, an IC driving method shown in FIG. 6 has been proposed.
The IC driving method shown in FIG. 6 has two sets of pin electronics circuits provided for one I/O pin of the IC under test 119, which are connected such that a drive signal path or line BL1 is connected between a driver DR1 of the first set of pin electronics circuit and an I/O pin 119A of the IC under test 119 and a response signal path or line BL2 is connected between the I/O pin 119A of the IC under test 119 and an input terminal of a comparator CP2 of the second set of pin electronics circuit. That is, it is constructed that the drive signal line BL1 and the response signal line BL2 are separated from each other, and an application of a drive signal and an acquisition of a response signal are performed through separate lines, respectively. The first set of pin electronics circuit comprises the driver DR1 and a comparator CP1, and the second set of pin electronics circuit comprises a driver DR2 and the comparator CP2.
It is assumed that a propagation delay time of the drive signal line BL1 is Tb and a propagation delay time of the response signal line BL2 is Tc. When the driver DR1 of the first set of pin electronics circuit outputs a test pattern signal PAT in the configuration shown in FIG. 6, this test pattern signal PAT arrives at the I/O pin 119A of the IC under test 119 at the timing that the propagation delay time Tb of the drive signal line BL1 has passed, and then arrives at the input terminal of the comparator CP2 of the second set of pin electronics circuit at the timing that the time duration equal to the sum Tb+Tc of the propagation delay time Tb of the drive signal line BL1 and the propagation delay time Tc of the response signal line BL2 has passed.
Consequently, in order to apply the test pattern signal PAT to the IC under test 119 from the beginning of the write cycle W, as shown in FIG. 7, even if the test pattern signal PAT is outputted at the timing preceding the starting timing of the write cycle W by the time duration equal to the propagation delay time Tb (FIG. 7D), this test pattern signal PAT arrives at the input terminal of the comparator CP2 of the second set of pin electronics circuit at the timing that the time duration of Tb+Tc has passed so that only the response signal D0 (FIG. 7B) can continue to be supplied to the input terminal of the comparator CP2. In other words, in this case, the dead time DT shown in FIG. 5 does not exist. As a result, even if the timing of generating a strobe pulse STB (FIG. 7C) is set throughout the time range that the response signal D0 outputted from the IC under test 119 exists, the comparator CP2 can acquire the response signal D0 at all timings.
As mentioned above, if the IC driving method shown in FIG. 6 is used, any dead time DT does not exist. Accordingly, even if the test cycle T is decreased to perform the test at high speed, the comparator CP2 of the second set of pin electronics circuit can surely acquire the response signal D0 from the IC under test 119, and hence a high-speed testing can be materialized.
As is apparent from the above description, in order to materialize a high-speed IC testing apparatus, the IC driving method shown in FIG. 6 is indispensable. In addition, in order to carry out the test at high speed, it is necessary to shorten the test cycle T, accompanied by the timing of applying the strobe pulse STB and the timing of generating the test pattern signal PAT being strictly controlled within the range of a minute time duration. For this end, it is also necessary to grasp accurate values of the propagation delay time Tb of the drive signal line BL1 and the propagation delay time Tc of the response signal line BL2.
From the structure of the aforementioned IC testing apparatus, the sum Tb+Tc of the propagation delay time Tb of the drive signal line BL1 and the propagation delay time Tc of the response signal line BL2 can easily be measured by utilizing the function of the response time measuring device 120. For example, it is sufficient to output a pulse from the driver DR1 of the first set of pin electronics circuit and to measure the time duration from the time point at which the pulse has been outputted until the pulse arrives at the input of the comparator CP2 of the second set of pin electronics circuit. Accordingly, the sum Tb+Tc of the propagation delay times can be measured by applying the strobe pulse STB to the comparator CP2 with the phase of the strobe pulse STB sequentially shifted in the lagging direction of the phase from the timing at which the pulse has been outputted from the driver DR1 and detecting a timing when an output of the comparator CP2 rises up to the logical H.
In this manner, the sum total Tb+Tc of the propagation delay times can easily be measured by the IC testing apparatus as constructed above. However, it is difficult in the IC testing apparatus as constructed above to measure the propagation delay times Tb and Tc separately from each other.
In order to accurately measure the response time of the IC under test 119, the timing of applying the strobe pulse STB and the timing of generating the test pattern signal PAT must accurately be controlled. From this viewpoint, it is necessary to accurately grasp the values of the propagation delay times Tb and Tc separately.
As one method for solving this problem, the assignee of the present application has proposed an invention entitled xe2x80x9cCIRCUIT FOR MEASURING A PROPAGATION DELAY TIME OF A TRANSMISSION PATHxe2x80x9d (Japanese Patent Application No. 189859/1994) disclosed in Japanese Patent Application Public Disclosure No. 36037/1996. The propagation delay time measuring circuit disclosed in this Patent Application Public Disclosure No. 36037/1996 adopts a method in which, as shown in FIG. 8, the one I/O pin 119A of an IC under test 119 is grounded, a drive pulse is outputted from the driver DR1 of the first set of pin electronics circuit or from the driver DR2 of the second set of pin electronics circuit, a reflected wave of this drive pulse is detected by the comparator CP1 connected in common with the driver DR1 of the first pin electronics or by the comparator CP2 connected in common with the driver DR2 of the second set of pin electronics circuit, and the respective propagation delay times Tb and Tc of the drive signal line BL1 and the response signal line BL2 are measured.
In the circuit for measuring a propagation delay time of a transmission path in the above patent application, the I/O pin 119A of the IC under test 119 must be grounded. It is impossible to perform this grounding work by manual operation. Next, the reason thereof will be described.
An IC testing apparatus is constructed such that many ICs under test are automatically transported using an IC transporting and handling apparatus called xe2x80x9chandlerxe2x80x9d in this technical field, a plurality of ICs, for example, 8 ICs, 16 ICs, 32 ICs or so are mounted at one time on IC sockets provided on the test head already described, and are tested at the same time.
In the IC testing apparatus constructed as such, it is difficult to ground the I/O pin by handwork only in case of measuring the propagation delay times Tb and Tc. However, as one method that can be taken, there is conceived a method in which dummy ICs in each of which the I/O pin is internally connected to a ground circuit are transported by the handler, and the measurement of the propagation delay times Tb and Tc is carried out in the state that these dummy ICs are mounted on respective IC sockets of the test head.
As shown in FIG. 9, within the test head TH of the IC testing apparatus are accommodated pin cards (pin electronics parts) on each 124 of which circuits and the like including the driver group 116 and the comparator group 117 of the IC testing apparatus TES are formed, as already described, and the performance board 125 is mounted on the top portion of the test head TH. A predetermined number of IC sockets SK are mounted on the upper portion of the performance board 125, and the number of terminals of each of the IC sockets corresponds to the number of pins of the IC under test 119. Usually, the IC sockets SK are secured to the performance board 125, and accordingly, in case of changing the type of ICs to be tested, a performance board having IC sockets corresponding to ICs of new type must be used, which results in that the entire performance board must be replaced by new one.
For this reason, a plurality of performance boards have been added to an IC testing apparatus as accessories, and it is necessary to measure the propagation delay times Tb and Tc for each of the performance boards added to the IC testing apparatus. It is sufficient to carry out the measurement of the propagation delay times Tb and Tc once in the state that the performance board 125 is mounted on the test head TH. However, many drive signal lines BL1, for example, such as 1000 lines or so are formed on the performance board 125, and the same number of response signal lines BL2 are also formed on this performance board 125 (in general, a signal line is called xe2x80x9cchannelxe2x80x9d). Accordingly, there is a drawback that the measurement of the propagation delay times Tb and Tc requires a very long time and much workload, resulting in a very troublesome work.
It is an object of the present invention to provide an IC testing apparatus which is capable of accurately measuring respective propagation delay times of a drive signal transmission path and a response signal transmission path separately from each other without need for grounding an input/output terminal of an IC under test, and of correctly testing a high-speed IC.
It is another object of the present invention to provide a method of measuring a propagation delay time of a transmission path in an IC testing apparatus, which is capable of accurately measuring respective propagation delay times of a drive signal transmission path and a response signal transmission path in a short time duration and separately from each other without need for mounting an IC under test on an IC socket.
In order to accomplish the aforesaid objects, in one aspect of the present invention, there is provided a propagation delay time measuring method in a semiconductor integrated circuit testing apparatus wherein a test pattern signal is supplied from a driver to an input/output terminal of a semiconductor integrated circuit under test through a first signal transmission path connected between the input/output terminal of the semiconductor integrated circuit under test and the driver, a response signal from the semiconductor integrated circuit under test outputted from the input/output terminal is inputted to a comparator through a second signal transmission path connected between the input/output terminal and the comparator, and whether the response signal outputted from the semiconductor integrated circuit under test coincides with a predetermined expected value or not is tested in a logical comparator means connected to the output side of the comparator, the aforesaid measuring method comprising the steps of: forming the first and the second signal transmission paths such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible; supplying a pulse signal from the driver to the first signal transmission path; detecting a timing when the pulse signal is outputted from the second signal transmission path, thereby to measure a propagation delay time caused by the first and the second signal transmission paths when the pulse signal has propagated therethrough; and determining a time duration equal to xc2xd of the measured propagation delay time to be a propagation delay time of each of the first and the second signal transmission paths.
In a preferred embodiment, the aforesaid step of detecting a timing when the pulse signal is outputted from the second signal transmission path applies strobe pulses the phases of which are sequentially lagged to the comparator connected to the second signal transmission path, and detects the rising timing of the pulse signal inputted to the comparator, and the aforesaid step of measuring a propagation delay time measures the propagation delay time caused by the first and the second signal transmission paths when the pulse signal has propagated therethrough on the basis of the timing at which the pulse signal is supplied from the driver to the first signal transmission path and the rising timing of the pulse signal inputted to the comparator.
According to the aforesaid propagation delay time measuring method, since a propagation delay time of a pulse signal propagating through both the first and the second signal transmission paths is measured, and a time duration equal to xc2xd of the measured value is determined to be a propagation delay time of each of the first and the second signal transmission paths, it suffices to simply input a pulse signal into either one of the first and the second signal transmission paths, thereby to input the pulse signal into the comparator connected to the other side of the series connected first and second signal transmission paths, and to detect a receiving timing of the pulse signal in the comparator based on the timing of supplying a strobe pulse, without need for grounding an input/output terminal of the semiconductor integrated circuit under test or without need for mounting the semiconductor integrated circuit under test on an IC socket.
In a second aspect of the present invention, there is provided a propagation delay time measuring method in a semiconductor integrated circuit testing apparatus wherein a test pattern signal is supplied from a driver to an input/output terminal of a semiconductor integrated circuit under test through a first signal transmission path connected between the input/output terminal of the semiconductor integrated circuit under test and the driver, a response signal from the semiconductor integrated circuit under test outputted from the input/output terminal is inputted to a comparator through a second signal transmission path connected between the input/output terminal and the comparator, and whether the response signal outputted from the semiconductor integrated circuit under test coincides with a predetermined expected value or not is tested in a logical comparator means connected to the output side of the comparator, the aforesaid measuring method comprising the steps of: forming the first and the second signal transmission paths such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible; supplying a pulse signal from the driver to the first signal transmission path; reflecting the pulse signal outputted from the second signal transmission path after having propagated through the first signal transmission path and the second signal transmission path to input the reflected pulse signal into the second signal transmission path; detecting a timing when the pulse signal is outputted from the first signal transmission path after having propagated through the second signal transmission path and the first signal transmission path, thereby to measure a propagation delay time caused by the first and the second signal transmission paths when the pulse signal has propagated therethrough in both ways; and determining a time duration equal to xc2xc of the measured propagation delay time to be a propagation delay time of each of the first and the second signal transmission paths.
In a preferred embodiment, the aforesaid step of detecting a timing when the pulse signal is outputted from the first signal transmission path applies strobe pulses the phases of which are sequentially lagged to a comparator connected to the first signal transmission path, and detects the rising timing of the pulse signal inputted to the comparator, and the aforesaid step of measuring a propagation delay time measures the propagation delay time caused by the first and the second signal transmission paths when the pulse signal has propagated therethrough in both ways on the basis of the timing at which the pulse signal is supplied from the driver to the first signal transmission path and the rising timing of the pulse signal inputted to the comparator connected to the first signal transmission path.
In addition, the aforesaid step of reflecting the pulse signal outputted from the second signal transmission path to input the reflected pulse signal into the second signal transmission path includes the step of reflecting the pulse signal at the output end of a driver connected to the second signal transmission path.
In a third aspect of the present invention, there is provided a semiconductor integrated circuit testing apparatus wherein a test pattern signal is supplied from a driver to an input/output terminal of a semiconductor integrated circuit under test through a first signal transmission path connected between the input/output terminal of the semiconductor integrated circuit under test and the driver, a response signal from the semiconductor integrated circuit under test outputted from the input/output terminal is inputted to a comparator through a second signal transmission path connected between the input/output terminal and the comparator, and whether the response signal outputted from the semiconductor integrated circuit under test coincides with a predetermined expected value or not is tested in a logical comparator means connected to the output side of the comparator, the aforesaid testing apparatus comprising: means for forming the first and the second signal transmission paths such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible; means for outputting a pulse signal from the driver at a known timing and inputting the pulse signal into the first signal transmission path; means for measuring a propagation delay time given to the pulse signal when the pulse signal has sequentially propagated through the first and the second signal transmission paths; and propagation delay time determining means for determining a time duration equal to xc2xd of the measured propagation delay time to be a propagation delay time of each of the first and the second signal transmission paths.
In a preferred embodiment, the aforesaid means for measuring a propagation delay time applies strobe pulses the phases of which are sequentially lagged to the comparator connected to the second signal transmission path, thereby to detect the rising timing of the pulse signal inputted to the comparator, and measures the propagation delay time given to the pulse signal when the pulse signal has propagated through the first and the second signal transmission paths on the basis of the detected rising timing of the pulse signal and the known timing of the pulse signal inputted into the first signal transmission path from the driver.
In addition, as the means for measuring a propagation delay time is used response time measuring means for measuring a response time of a semiconductor integrated circuit under test, which is provided in the aforesaid semiconductor integrated circuit testing apparatus.
Moreover, the first and the second signal transmission paths may be formed such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible by forming a wiring pattern of the first signal transmission path on a printed board of one layer of a performance board constructed by a multi-layered printed board to be mounted on a test head of the aforesaid semiconductor integrated circuit testing apparatus, copying this wiring pattern on a printed board of an adjacent one layer, thereby to form the wiring pattern of the same shape on the printed board of this adjacent layer, and using these wiring patterns as the first signal transmission path and the second signal transmission path, respectively.
Alternatively, the first and the second signal transmission paths may be formed such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible by using cables having the same length as the first signal transmission path and the second signal transmission path, and by connecting between an input/output terminal of the semiconductor integrated circuit under test and the driver, and between the input/output terminal of the semiconductor integrated circuit under test and the comparator by use of the cables, respectively, on a performance board to be mounted on a test head of the aforesaid semiconductor integrated circuit testing apparatus.
In a fourth aspect of the present invention, there is provided a semiconductor integrated circuit testing apparatus wherein a test pattern signal is supplied from a driver to an input/output terminal of a semiconductor integrated circuit under test through a first signal transmission path connected between the input/output terminal of the semiconductor integrated circuit under test and the driver, a response signal from the semiconductor integrated circuit under test outputted from the input/output terminal is inputted to a comparator through a second signal transmission path connected between the input/output terminal and the comparator, and whether the response signal outputted from the semiconductor integrated circuit under test coincides with a predetermined expected value or not is tested in a logical comparator means connected to the output side of the comparator, the aforesaid testing apparatus comprising: means for forming the first and the second signal transmission paths such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible; means for outputting a pulse signal from the driver at a known timing and inputting the pulse signal into the first signal transmission path; means for reflecting the pulse signal outputted from the second signal transmission path after having propagated through the first signal transmission path and the second signal transmission path in regular sequence to input the reflected pulse signal into the second signal transmission path; means for measuring a propagation delay time given to the pulse signal when the pulse signal has propagated through the first signal transmission path and the second signal transmission path in both ways; and propagation delay time determining means for determining a time duration equal to xc2xc of the measured propagation delay time to be a propagation delay time of each of the first and the second signal transmission paths.
In a preferred embodiment, the aforesaid means for measuring a propagation delay time applies strobe pulses the phases of which are sequentially lagged to a comparator connected to the first signal transmission path, thereby to detect the rising timing of the reflected pulse signal inputted to the comparator after having been outputted from the first signal transmission path, and measures the propagation delay time given to the pulse signal when the pulse signal has propagated through the first and the second signal transmission paths in both ways on the basis of the detected rising timing of the reflected pulse signal and the known timing of the pulse signal inputted into the first signal transmission path from the driver.
In addition, as the aforesaid means for measuring a propagation delay time is used response time measuring means for measuring a response time of a semiconductor integrated circuit under test, which is provided in the aforesaid semiconductor integrated circuit testing apparatus.
The pulse signal outputted from the second signal transmission path is reflected at the output end of a driver connected to the second signal transmission path and is inputted into the second signal transmission path.
Moreover, the first and the second signal transmission paths may be formed such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible by forming a wiring pattern of the first signal transmission path on a printed board of one layer of a performance board constructed by a multi-layered printed board to be mounted on a test head of the aforesaid semiconductor integrated circuit testing apparatus, copying this wiring pattern on a printed board of an adjacent one layer, thereby to form the wiring pattern of the same shape on the printed board of this adjacent layer, and using these wiring patterns as the first signal transmission path and the second signal transmission path, respectively.
Alternatively, the first and the second signal transmission paths may be formed such that a length of the first signal transmission path and a length of the second signal transmission path have a ratio of 1:1 as much as possible by using cables having the same length as the first signal transmission path and the second signal transmission path, and by connecting between an input/output terminal of the semiconductor integrated circuit under test and the driver, and between the input/output terminal of the semiconductor integrated circuit under test and the comparator by use of the cables, respectively, on a performance board to be mounted on a test head of the aforesaid semiconductor integrated circuit testing apparatus.